1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device in which is formed a MOS FET (Metal-Oxide-Semiconductor Field Effect Transistor) having a trench structure, and a semiconductor device suitably manufactured through the manufacturing method.
2. Description of Related Art
A semiconductor device includes a type provided with a MOS FET (MOS Field Effect Transistor) having a trench structure. In a semiconductor device of this type, a source region and a channel region are placed along the depth direction of the trench, which makes it possible to achieve miniaturization of elements and a reduction of power consumption.
FIG. 3 is a schematic cross section showing a structure of a semiconductor device provided with a MOS FET having the trench structure, obtained through a conventional manufacturing method.
An Nxe2x88x92 epitaxial layer 52 is formed on the surface of a silicon substrate 51, and a diffusion region 65 is formed on the Nxe2x88x92 epitaxial layer 52. Trenches 54, each of which penetrates through the diffusion region 65 and halfway through the Nxe2x88x92 epitaxial layer 52 in the thickness direction, are formed at regular intervals. Inside each trench 54 is provided a gate electrode 55 made of polysilicon, and a gate oxide film 56 is provided to surround the gate electrode 55.
N+ source regions 57 and P+ base regions 58 are formed in the surface layer portion of the diffusion region 65, and the rest of the diffusion region 65 forms a Pxe2x88x92 channel region 53. The N+ source regions 57 are formed on the periphery (rim portion) of each trench 54. The P+ base region 58 is formed between every two adjacent N+ source regions 57, and is connected to the Pxe2x88x92 channel region 53.
Insulation films 59 made of silicon oxide are formed to cover above each trench 54. The insulation films 59 are also present on the periphery of each trench 54 (on the N+ source regions 57) when viewed in a plane. A space between every two adjacent insulation films 59 forms a contact hole 60. An electrode film 61 made of metal, such as aluminum, is formed on the diffusion region 65 and the insulation films 59. The electrode film 61 is placed to fill in the contact holes 60.
While the semiconductor device described above is operating, a current flows from the N+ source regions 57 toward the silicon substrate 51 through the Pxe2x88x92 channel region 53 along the gate oxide films 56.
FIG. 4(a), FIG. 4(b), and FIG. 4(c) are schematic cross sections used to explain a manufacturing method of the semiconductor device of FIG. 3.
Initially, the Nxe2x88x92 epitaxial layer 52 is formed on the silicon substrate 51. Then, impurities used to control a conduction type to be a p-type are introduced into the surface layer portion of the Nxe2x88x92 epitaxial layer 52, whereby the Pxe2x88x92 channel region 53 is formed. Subsequently, the P+ base regions 58 and the trenches 54 are formed. Although it does not matter which of the P+ base regions 58 and the trenches 54 are formed first, the following description will describe a case where the P+ regions 58 are formed first.
A mask layer 71 having openings (hereinafter, referred to as base-region forming openings) 70 in portions corresponding to the P+ base regions 58 is formed on the Pxe2x88x92 channel region 53. Then, impurities are implanted and diffused into the Pxe2x88x92 channel region 53 through the base-region forming openings 70, whereby the P+ base regions 58 are formed (FIG. 4(a)). The mask layer 71 is then removed. Subsequently, the N+ source regions 57 are formed through the same method using another mask layer having openings.
Then, a first resist film 73 having openings (hereinafter, referred to as trench forming openings) 72 in portions corresponding to the trenches 54 is formed on the Pxe2x88x92 channel region 53. Then, the N+ source regions 57, the Pxe2x88x92 channel region 53, and the upper portion of the Nxe2x88x92 epitaxial layer 52 are etched away through the trench forming openings 72, whereby the trenches 54 are formed (FIG. 4(b)). The first resist film 73 is then removed, and the inner wall surface of each trench 54 is subjected to thermal oxidation, whereby the gate oxide film 56 is formed.
Then, a polysilicon film is formed to fill in the trenches 54. Impurities are introduced into the polysilicon film to make the polysilicon film electrically conductive, whereby the gate electrodes 55 are formed. The top surfaces of the respective gate electrodes 55 are flush with the surfaces of the P+ base regions 58 and the N+ source regions 57.
Subsequently, a silicon oxide film 76 is formed across the entire surface of the silicon substrate 51 having undergone the foregoing processes. A second resist film 75 having openings 74 in portions corresponding to the contact holes 60 is then formed on the silicon oxide film 76 (FIG. 4(c)). The silicon oxide film 76 is etched away through the openings 74 of the second resist film 75, whereby the contact holes 60 are formed. Residual portions of the silicon oxide film 76 form the insulation films 59. After the second resist film 75 is removed, the electrode film 61 is formed on the silicon substrate 51 having undergone the foregoing processes. The semiconductor device shown in FIG. 3 is thus obtained.
The base-region forming openings 70 and the trench forming openings 72 are formed through the lithographic technique using a stepper (exposure apparatus). For this reason, the trench forming openings 72 are aligned and formed so that the trenches 54 will be formed at predetermined positions with respect to the P+ base regions 58.
Also, the openings 74 used to form the contact holes 60 are aligned and formed so as to avoid portions above the trenches 54 (gate electrodes 55).
Referring to FIG. 3, because the P+ base regions 58 need to be spaced apart from the gate oxide films 56, the base-region forming openings 70 are aligned with accuracy within a diffusion margin Md, which is equal to intervals between the P+ base regions 58 at the predetermined positions and the gate oxide films 56. Also, because the insulation films 59 need to be present between the respective gate electrodes 55 and the electrode film 61, the contact holes 60 are aligned with accuracy within a contact margin Mc, which is equal to intervals between the contact holes 60 at adequate positions and the gate electrodes 55.
Incidentally, in order to meet the demand to reduce power consumption of the power MOS FET, miniaturization of cell pitches has been advancing recently, and the diffusion margin Md and the contact margin Mc are also becoming smaller. On the other hand, according to the manufacturing method as described above, for example, a shift in alignment of approximately 0.3 xcexcm is inevitably caused during exposure by the exposure apparatus. For these reasons, it has been becoming difficult to form a microscopic MOS FET having a trench structure through the method described above.
It is therefore an object of the invention to provide a manufacturing method of a semiconductor device, capable of manufacturing a semiconductor device provided with a microscopic MOS FET having a trench structure.
Another object of the invention is to provide a semiconductor device provided with a MOS FET having a trench structure that can be miniaturized.
A manufacturing method of a semiconductor device of the invention is a method of manufacturing a semiconductor device provided with a MOS field effect transistor having a channel region of a first conduction type formed in a surface layer portion of a semiconductor substrate, a source region of a second conduction type formed on a rim portion of a trench made to penetrate through the channel region, and a base region of the first conduction type formed in the surface layer portion of the semiconductor substrate adjacently to the source region. The method includes: a step of introducing impurities used to control a conduction type to be the first conduction type into the surface layer portion of the semiconductor substrate in order to form the channel region; a step of forming a mask layer having a base-region forming opening corresponding to the base region and a trench forming opening corresponding to the trench on the semiconductor substrate in which the channel region is formed; a step of introducing the impurities used to control a conduction type to be the first conduction type into a surface layer portion of the channel region through the base-region forming opening in the mask layer in order to form the base region; a step of forming the trench that penetrates through the channel region by etching away the surface layer portion of the semiconductor substrate through the trench forming opening in the mask layer; and a step of forming a gate insulation film on an inner wall surface of the trench.
According to the invention, the positions of the base region and the trench in the surface layer portion of the semiconductor substrate are determined by the base-region forming opening and the trench forming opening made in the mask layer. Hence, for example, in a case where the base region is formed first and then the trench is formed, the trench is formed while being aligned exactly with respect to the base region. Likewise, in a case where the trench is formed first, and then the base region is formed, the base region is formed while being aligned exactly with respect to the trench. The trench forming opening and the trench together form a single concave having a continuous inner sidewall surface.
When the base region is formed, for example, the impurities may be introduced through the base-region forming opening by temporarily filling the trench forming opening with resist or the like. Likewise, when the trench is formed, for example, the surface layer portion of the semiconductor substrate may be etched away by temporarily filling the base-region forming opening with resist or the like. The resist is removed after the base region or the trench is formed.
As has been described above, according to the manufacturing method of the semiconductor device, the base region and the trench are aligned automatically (self-aligned), and a process for performing exact alignment is no longer needed. It is thus possible to manufacture a semiconductor device provided with a microscopic MOS FET having a trench structure.
It is preferable that the method further includes: a step of forming a polysilicon film in a region from inside the trench to a lower portion inside the trench forming opening and at a lower portion inside the base-region forming opening; a step of making the polysilicon film electrically conductive by introducing impurities into the polysilicon film; a polysilicon film oxidizing step of forming a silicon oxide film by oxidizing, of the polysilicon film, an upper portion of the polysilicon film inside the trench, the polysilicon film inside the trench forming opening, and the polysilicon film inside the base-region forming opening; a step of forming resist on the silicon oxide film inside the trench forming opening and inside the base-region forming opening after the polysilicon film oxidizing step; a step of forming a source-region forming opening corresponding to the source region between the base region and the trench by etching away the mask layer using the resist as a mask; and a step of introducing impurities used to control a conduction type to be the second conduction type into the surface layer portion of the channel region through the source-region forming opening in order to form the source region.
For example, the polysilicon film may be formed on the semiconductor substrate entirely, and removed through etching, so that the polysilicon film is only left and formed inside the trench, at the lower portion inside the trench forming opening, and at the lower portion inside the base-region forming opening.
In the step of oxidizing the polysilicon film, a silicon oxide film is formed in a portion from the upper portion of the trench to the lower portion of the trench forming opening. By forming an electrode film in the step later so as to cover above the silicon oxide film, the silicon oxide film then lies between the gate electrode and the electrode film. Hence, the silicon oxide film thus obtained can be used as an insulation film. The electrode film can be formed in such a manner so as to be connected to the source region through the use of a space between two adjacent insulation films as a contact hole.
Of the polysilicon film that is made electrically conductive through introduction of impurities, part of the polysilicon film inside the trench is not oxidized and left intact as polysilicon. The polysilicon thus left forms a gate electrode.
The gate electrode and the insulation film are both obtained from the polysilicon film that is formed inside the concave formed by the trench forming opening and the trench. Hence, the insulation film is formed directly above the gate electrode, and the side surface of the insulation film extends from the inside to the outside of the trench along the inner sidewall surface of the trench.
As has been described, the insulation film is formed while being aligned automatically with respect to the trench. Hence, the contact hole is formed while being aligned automatically with respect to the trench, etc.
Further, because the source-region forming opening is formed in such a manner that the opening portion (the base-region forming opening and the trench forming opening) and the non-opening portion of the mask layer are inverted, the position of the source region is also determined by the mask layer. Hence, the source region is formed while being aligned automatically with respect to the base region and the trench.
As has been described, according to the manufacturing method of the semiconductor device, the base region, the trench, the source region, and the insulation film (contact hole) are aligned automatically, and a step of performing exact alignment is no longer needed. It is thus possible to manufacture a semiconductor device provided with a microscopic MOS FET having a trench structure.
The mask layer may be a layer having resistance to an etching medium used in the trench forming step, and for example, it may be a layer made of silicon oxide. In this case, for example, the trench can be formed through dry etching.
A semiconductor device of the invention includes: a channel region of a first conduction type formed in a surface layer portion of a semiconductor substrate; a source region of a second conduction type formed on a rim portion of a trench made to penetrate through the channel region; a base region of the first conduction type formed in the surface layer portion of the semiconductor substrate adjacently to the source region; a gate insulation film formed on an inner sidewall surface of the trench; a gate electrode placed inside the trench to oppose the channel region with the gate insulation film in between; and an insulation film provided from an inside to an outside of the trench above the gate electrode and having a side surface extending along an inner sidewall surface of the trench from the inside to the outside of the trench.
The above and other objects, features, and advantages of the invention will become more apparent from the following description of embodiments with reference to the accompanying drawings.